12/28/2023 0 Comments Memory barrier cache coherence![]() G06F12/08- Addressing or allocation Relocation in hierarchically structured memory systems, e.g.G06F12/02- Addressing or allocation Relocation.G06F12/00- Accessing, addressing or allocating within memory systems or architectures.G06- COMPUTING CALCULATING OR COUNTING.Assignors: BRIDGE CROSSING, LLC Application granted granted Critical Publication of US9141545B2 publication Critical patent/US9141545B2/en Status Active legal-status Critical Current Anticipated expiration legal-status Critical Links ![]() Publication of US20150089157A1 publication Critical patent/US20150089157A1/en Assigned to ARM FINANCE OVERSEAS LIMITED reassignment ARM FINANCE OVERSEAS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BERG, THOMAS BENJAMIN, LEE, WILLIAM Assigned to BRIDGE CROSSING, LLC reassignment BRIDGE CROSSING, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Application filed by ARM Finance Overseas Ltd filed Critical ARM Finance Overseas Ltd Priority to US14/557,715 priority Critical patent/US9141545B2/en Assigned to MIPS TECHNOLOGIES, INC. Original Assignee ARM Finance Overseas Ltd Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) ( en Inventor William Lee Thomas Benjamin Berg Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Active Application number US14/557,715 Other versions US20150089157A1 Google Patents Speculative read in a cache coherent microprocessorĭownload PDF Info Publication number US9141545B2 US9141545B2 US14/557,715 US201414557715A US9141545B2 US 9141545 B2 US9141545 B2 US 9141545B2 US 201414557715 A US201414557715 A US 201414557715A US 9141545 B2 US9141545 B2 US 9141545B2 Authority US United States Prior art keywords request speculative coherent entry memory Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US9141545B2 - Speculative read in a cache coherent microprocessor 9141545B2 - Speculative read in a cache coherent microprocessor When processor 2 read flag is true, the memory consistency contract must guarantees producer() running on processor 1 already write product to 1. Code example producer-consumer concurrentĪfter processor 1 call producer() write product to 1, the cache coherence protocol ensure processor 2 read product must be 1. What properties must be enforced among reads and writes by different processors?Ĭache coherence and memory consistency are complementary: coherence defines the behavior of reads and writes to same memory location, consistency defines the behavior of reads and writes of different memory location.What order must a processor observe (by read) the data writes by other processor?.How consistent: When a processor see a value that been updated by another processor?.Cache coherence: multi-processor see a consistent view of memory.Ĭonnection between cache coherence and memory consistency Weak consistency: the reordering only subject to data dependencies and explicit memory barrier.Relaxed consistency: some type of the reordering are allowed.Sequential consistency: all reads and writes in binary program order.Memory consistency of processor and memory model of programming language is same thing in different layer.The accessing memory result will be predictable if following the rule. The rule or contract keep correctness for concurrent objects (single core's out-of-order and multi-issue execution, multi-core's memory operation on shared memory).(consistency means the quality of always behaving or performing in a similar way) The rule or contract between processor and system programmer or compiler writer, which constrain the reordering of memory access instructions at run-time. (coherence means fit together) Cache coherence protocol : The protocol implement in cache subsystem guarantees the data of same address on different processor's private cache must be same, which ensure all core see a consistent view of memory and cache is transparent to programmer.
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